The applicant of the present application has previously developed a timing generator circuit as shown in FIG. 1 that can be used, for example, for a dynamic RAM (random-access memory). In this timing generator circuit, a bootstrap voltage is shaped by utilizing an input timing signal .phi..sub.in and an inverted delay signal thereof, and an output MOSFET Q55 on the power-source voltage side is driven to obtain an output signal at the level of the power-source voltage. According to this timing generator circuit, an output of a predetermined low level is formed when push-pull MOSFETs Q53, Q54 and output MOSFETs Q55, Q56 in a drive stage and an output stage are turned on during a delay time defined from when the input timing signal .phi..sub.in reaches a high level to when the inverted delay signal thereof reaches a low level. Therefore, a relatively large through-current flows, resulting in an increased consumption of current. When the output terminal is provided with a bootstrap capacitor CB2 to raise the output signal to a level higher than that of the power-source voltage V.sub.CC, a MOSFET Q57 which is supplied with the power-source voltage V.sub.CC at all times through the gate thereof is also provided, to ensure the withstand voltage of the output MOSFET Q56 with respect to high-level output signals. In order to produce a low-level output as described above, therefore, the ratio of the conductance of the MOSFET Q55 on the power-source voltage side to the total conductance of the serially connected MOSFETs Q56, Q57 must be large. Therefore, the size of the output MOSFETs Q56, Q57 on the ground-potential side must be extremely large, necessitating a relatively large layout area therefor.
A dynamic RAM which requests such a timing generator circuit is described in detail in Japanese Patent Laid-Open No. 82282/1982 and Japanese patent application No. 164831/1982.